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The purpose of this paper is to find a closed relation for the phase noise of LC oscillators.

The governing equation of oscillators is generally a stochastic nonlinear differential equation. In this paper, a closed relation for the phase noise of LC oscillators was obtained by approximating the I–V characteristic of the oscillator with third-degree polynomials and analyzing its differential equation.

This relation expresses phase noise directly in terms of circuit parameters, including the sizes of the transistors and the bias. Next, for evaluation, the phase noise of the cross-coupled oscillator without tail current was calculated with the proposed model. In this approach, the obtained equations are expressed independently of technology by combining the obtained phase noise relation and g_m/I_D method.

A technology-independent method using the g_m/I_D method and the closed relationship is provided to calculate phase noise.

This paper aims to find a closed-form expression for the frequency and amplitude of single-ended ring oscillators when transistors experience all regions.

In this paper, the analytical relationships presented for ring oscillator amplitude and frequency are approximately derived due to the nonlinear nature of this oscillator, taking into account the differential equation that governs the ring oscillator and its output waveform.

In the case where the transistors experience the cut-off region, the relationships presented so far have no connection between the frequency and the dimensions of the transistor, which is not valid in practice. The relationship is presented for the frequency, including the dimensions of the transistor. Also, a simple and approximately accurate relationship for the oscillator amplitude is provided in this case.

The validity of these relationships has been investigated by analyzing and simulating a single-ended oscillator in 0.18 µm technology.

The linear analysis presented for the charge pump phase locked loops (CPPLLs) becomes inaccurate or incorrect where cycle slipping occurs. In this paper, an analytical approach is proposed, which explains the conditions in which cycle slipping happens. Using the analytical results, one can simply design or redesign a CPPLL to prevent or decrease cycle slipping and hence decreasing the locking time. The paper aims to discuss these issues.

To obtain cycle slipping conditions, CPPLL's signals in the time domain are tracked and cycle slipping condition is investigated. Based on the proposed analysis, by comparing a simple function of system's parameters with a threshold, cycle slipping is predicted.

The cycle slipping conditions are expressed in terms of system's parameters and the size of the input frequency step. The method is also generalized for a fast CPPLL with an aid-lock BBFC circuit. The good accuracy of the analytical predictions is verified using simulations in Matlab/Simulink.

A new analytical method for cycle slipping prediction in CPPLLs is presented. A closed form equation in terms of system's parameters and input frequency step has been presented, which can predict the cycle slipping possibility in the system without a need to perform the full time-consuming simulations. This analytical method that uses the LambertW function's properties proposes a threshold to predict cycle slipping in the system. This method not only can be used by designers to predict cycle slipping but can also be used to design the CPPLL in order to remove or decrease cycle slipping. The method is also generalized for fast locking charge pump PLLs and as a case study, cycle slipping prediction in the BBFC-CPPLL is performed.

Bang-bang clock and data recovery (BBCDR) circuits are hard nonlinear systems due to the nonlinearity introduced by the binary phase detector (BPD). The specification of the CDR frequency response is determined by jitter tolerance and jitter transfer. In this paper, jitter transfer and jitter tolerance of the BBCDR are characterized. The paper aims to discuss these issues.

The presented method is general enough to be used for designing the BBCDR loop parameters to meet SONET jitter transfer requirements (loop bandwidth and jitter peaking).

In this paper, jitter transfer and jitter tolerance of the BBCDR are characterized by formulating the time domain waveforms. As a result, a new equation is presented to obtain angular frequency. Also, the jitter tolerance is expressed in closed form as a function of loop parameters. The validity of the resulted equations is verified through HSPICE simulations using TSMC 0.18-μm CMOS process. Simulation results show that good conformance between analytical equations and simulation results.

The proposed approach offers two advantages compared to conventional designing methods. First, this approach does not consider any value restriction to the capacitor. Second, a new condition has been presented to guarantee that the value of jitter peaking is approximately zero. The presented method is general enough to be used for designing the BBCDR.